Differential signaling is a method of transmitting signals over a pair of wires for reducing the noise on an electrical connection by rejecting common-mode interference. Differential signaling is generally based upon the concept of a first wire carrying a first signal and a second wire carrying a second signal that is the inverse of the first signal. Thus, the sum of the voltages of the first and second wires is always constant. Typically, the first and second wires are close to one another so that they are subjected to the same interference.
A fully differential signal path is generally preferred in integrated analog circuitry, especially in high-frequency applications. One reason that utilizing a fully differential signal path is beneficial is due to its well-known properties of immunity to common-mode disturbances, rejection of parasitic couplings, and increased dynamic range. Often, it is necessary to convert a single signal to a differential signal to obtain these benefits. This can be done using a single-to-differential type converter.
In reference to FIG. 1, a prior art circuit diagram for a single-to-differential converter is generally shown at 10. The single-to-differential converter 10 has a first stage generally indicated at 12 and a second stage generally indicated at 14. A single-ended voltage signal Vn is applied at the input of the first stage 12. The differential voltage signals Vout are outputted by the first stage 12 and received by the second stage 14. The asymmetric effect due to the differential signal path of the first stage 12 is compensated in the second stage 14.
However, the reference current source Iref is sensitive to the noise of the supply and the variation of the tail current of Iref will increase the time delay jitter, which results in a reduction in the phase noise performance. The bandwidth of the single-to-differential converter 10 can be increased with higher quiescent currents. The maximizing of the gain for a given quiescent current requires an increase in the aspect ratio of transistor devices (M1 and M2) and/or the increase of load resistor RL. However, the increase in the aspect ratio of M1 and M2 leads to an increase in output capacitance, which results in lower frequency response performance of the first stage 12. Further, larger load resistance of RL reduces the output swing due to the large voltage drops across it. Additionally, the single-to-differential converter 10 utilizing differential pair transconductance amplifiers results in difficulties in achieving wide-band performance in this design. Therefore, there is a trade-off amongst the gain, bandwidth, phase noise, and current consumption in the single-to-differential converter 10.
A software-defined radio (SDR) architecture generally requires wide-band support ranging from a few hundred mega-hertz to a few giga-hertz having a stringent phase noise performance offset with power consumption comparable to a single narrow-band architecture. As described herein, the single-to-differential converter 10 typically cannot operate at the above conditions. Therefore, the need exists to develop a single-to-differential stage that has a large bandwidth range and achieves low-power consumption with desirable phase noise performance.
Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.